1. Field of the Invention
This invention relates to electronic systems, and more particular, to circuitry for implementing parity trees.
2. Description of the Related Art
Computers and other digital systems utilize parity circuits in order to detect the presence of errors in transferred data. When data is transmitted, one or more extra bits may be appended onto the transmitted data for error checking purposes. The bits may be appended such that there is an even or an odd number of logic ones (or zeros) in the data. A parity checking circuit may receive the transmitted data and check to ensure that the data includes the correct number of ones or zeros.
Parity is typically checked by parity tree. The size of a parity tree is dependent on the size of the data for which parity is being checked. Thus, as digital systems are designed to process greater data sizes (e.g., 64 bit processors), the corresponding growth of parity trees increases the number of logic gates necessary to implement them, and may thus slow down the error-checking process. Thus, implementing parity trees with slow circuitry may reduce the overall speed at which the system for which parity is being checked may operate.